High Performance Gate Oxides
Reduce dielectric interfacial defects to improve gate oxide properties.
Key Gate Oxide Application Challenges
Effective Oxide Thickness
Smaller, more efficient devices require highly uniform nucleation and film growth on 3D structures. Doped silicon channel materials are reaching their physical limits for carrier mobility. New processes and precursors are needed for SiGe and 50/50% SiGe, which are early implementation.
When oxides are not deposited uniformly on gate structures, dangling bonds are left behind. This leads to dielectric leakage and poor electrical performance. Risk of this surface degradation associated with water increases with vertical scaling.
Germanium migration into the high K dielectric destroys high K properties. Processes must ensure that there is no germanium migration.
Solving Key Issues for Better Gate Oxides
Low Process Temperatures
Lower temperature processes prevent germanium migration and aid in removal of dangling bonds. Hydrogen peroxide gas is effective at temperatures as low as 300C
Densely Packed Oxidation
Ideally, the process oxidant will react with every silicon and germanium bond, eliminating surface dangling bonds and potential island growth. Hydrogen peroxide has lower steric hindrance than water and naturally forms hydroxyl groups, reducing dangling bonds.
Thin-Film Passivation Layer
High quality, thin, low defect interface layers can be created at low temperatures using hydrogen peroxide gas. Passivation layers are ultra-thin so that they do not compromise device properties.
See Latest Research on Oxides.
Introducing BRUTE® Peroxide
Water-Free Hydrogen Peroxide Gas
BRUTE Peroxide delivers virtually water-free Hydrogen Peroxide (H2O2) gas to process. This liquid solution of hydrogen peroxide and a proprietary solvent come pre-loaded in a RASIRC vaporizer. Hydrogen peroxide gas has a rapid and straightforward reaction path, making it superior to other oxidation methods.
Dielectric Layer Passivation and Functionalization
Hydrogen peroxide gas enables in situ low temperature surface passivation that reduces dielectric layer defects
In situ gas phase surface passivation of SiGe channel materials can improve gate stack fabrication in logic devices. The passivation layer prevents atomic migration of channel materials into other layers.
Passivation leaves the surface functionalized and ready for high k deposition.
Passivation layers must be ultra-thin so that they do not compromise high k properties. Typically 0.5 to 2 monolayers of passivation are desired. These layers must be uniformly deposited on three-dimensional structures such as FINFETs, MOSFETs and nanowire geometries.
Thin film deposition requires high conformality with nucleated growth in every unit cell. This high conformity ensures low defect density and low gate leakage.
The biggest challenge is achieving a high-quality interface between the substrate and the gate oxide.
The figure below demonstrates improved nucleation for BRUTE Peroxide over water and wet peroxide gas.
Reduce Interfacial Defects and Dielectric Leakage
Improve Device Performance, Yield and Reliability
Dry hydrogen peroxide gas can be used for in situ low temperature passivation. Studies show that this approach leads to fewer defects and better initiation layers for subsequent gate oxides.
Detrimental surface features that can be improved include:
- Dangling bonds on Ge and Si
- Ge-oxides with poor electrical properties
- Interlayer oxide defects that allow Ge migration into the High K dielectric
- Ge-Ge dimers
- High surface roughness
- Organic and carbon contamination
Unique Benefits for Surface Passivation and Functionalization of New Channel Materials
- Functionalizes surface with -OH groups at temperatures as low as 25C
- Minimizes surface penetration and GeOx formation, due to its anhydrous properties
- Removes residual organic molecular contamination
- Removes remaining surface dangling bonds and surface roughness with subsequent low temperature annealing at 300C. A thermodynamically stable, thin, uniform, high quality interlayer dielectric results.
BRUTE Peroxide Beats Traditional Vaporizers and Passivation Technology
- BRUTE Peroxide delivers up to 99.9% hydrogen peroxide particle-free gas by volume. No other commercial technology can deliver ultra-dry hydrogen peroxide gas.
- Plasma technology requires line of sight not possible in high aspect ratio devices
- Ozone gas can burn and damage surfaces
- Bubblers deliver less than 1% hydrogen peroxide gas by volume
- Flash vaporizers create hydrogen peroxide droplets that lead to particle formation on surfacesannealing at 300C. A thermodynamically stable, thin, uniform, high quality interlayer dielectric results.
BRUTE Peroxide Datasheet
PUBLISHED IN 2017
RASIRC BRUTE Peroxide provides a breakthrough method to deliver virtually water-free hydrogen peroxide (H2O2) gas into Atomic Layer Deposition (ALD) and Etch (ALE) processes. BRUTE Peroxide solution is preloaded in a RASIRC vaporizer. This solution combines hydrogen peroxide liquid and a proprietary solvent, which ensures that the liquid source remains below 30% by weight hydrogen peroxide.
Anhydrous Hydrogen Peroxide Gas Delivery for Atomic Layer Deposition
PUBLISHED IN 2016
In order to minimize defects, enhance uniformity and increase device performance, researchers have begun to focus on the interface between dielectric materials and Si, SiGe, Ge and InGaAs. Most defects, which lead to charge traps and decreased mobility, are believed to occur in this interfacial region. While cartoons of ALD show nice monolayer continuous growth, ALD growth usually occurs in islands on the surface with 3 cycles typically needed for each monolayer. More surprising is that initiation of ALD growth on the surface is far from ideal. Initial film growth of the first monolayer may take up to 6-7 cycles. Research suggests that significant device improvements can be made if the surface is functionalized with a dense layer of hydroxyl groups –OH, prior to deposition.
RASIRC to Present Anhydrous Hydrogen Peroxide Surface Preparation and Enhanced Nucleation for ASD at ASD2018
PUBLISHED ON APRIL 24, 2018
Area selective deposition is becoming increasingly important for the immense scaling effort continuously taking place in the semiconductor industry for Logic and Memory Devices. Today double and multiple pattering schemes using Plasma Enhanced ALD are in High Volume Manufacturing (HVM) for all sub 28 nm nodes and any moment now the industry expect to ramp EUV lithography, possibly at the 7 nm Foundry Node. Beyond that in a joint effort the researchers and the industry are looking for alternative patterning methods and many of them are based on so called bottom-up patterning.
RASIRC products generate and deliver water vapor, hydrogen peroxide and hydrazine gas in controlled, repeatable concentrations to critical processes.
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